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Emera Infotech Pvt Ltd , A subsidiary of avis Worldwide services is a forerunner in the field of hard-core technology promoted by enterprising technocrats with more than a decade of experience in the areas of VLSI, JAVA offering a wider range of solutions customized to various verticals and horizontals.Seamlessly integrating precision and ingenuity, Emera's abilities stem from our creative leadership in hard-core technology and strength in design with a mission that incorporates research, creative activity and service.
We are working in the design and developments of Communication protocols like USB, OTG, SPI, HDLC. Emera offers services in verification - comprising Reusable testbenches,BFM development, verification planning, constrained random based verification with functional coverage, Assertion based Verification, Layered Testbench. We have executed many successful verification projects to ensure zero functional bugs. Our customers in the space of complex SoC design have found value in our service capabilities - which is demonstrated with the repeat orders that we are enjoying.
We also have JAVA/J2EE team of expert professionals to develop various projects including enterprise java applications, server side java applications,webservices and business logic applications.
Services
Emera’s key objective is to provide organizations enterprise-wide, business process visibility & technology optimization by utilizing our proprietary methodologies. We will strive to deliver solutions high on innovation, all the time conscious of quality, time and cost and most of all designed according to your needs.
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VLSI DESIGN SERVICES
Design and verification of IP Cores |
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JAVA DEVELOPMENT
Your link to Smart Solutions |
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WEB DESIGN SERVICES
We design web sites that drives customers into it. |
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EMBEDDED SYSTEM DESIGN
Single-stop provider of hardware and software solutions |
VHDL Simulation & Synthesis
Introduction to VHDL
• The origins of VHDL VHDL basics Benefits of VHDL
• VHDL levels of abstraction
• Abstraction and timing
• VHDL in the system design flow
• The VHDL design flow
• VHDL synthesis
• Modelling hardware in VHDL VHDL design entities
• Entity declarations
• Architectures
• Using libraries and packages Concurrent signal assignments Signal assignments with delays
Hierarchy in VHDL
• Component declarations
• Component instantiation
• Named port mapping
• Positional port mapping
• Direct instantiation
• Configuration specifications
• Entity binding
• Port modes VHDL
• Processes
• Processes sensitivity lists Test benches
Objects and Data Types
• Objects in VHDL
• Constants, variables and signals
• VHDL types
• Scalar types
• Arrays
• Records
• Synthesis of ints and enums
• Custom types and subtypes
• Tristate and resolved types
• std_ulogic and std_logic
• unsigned and signed
• Attributes
Concurrent and Sequential Statements
• Concurrent statements
• Sequential statements
• Conditional & selective signal assignments
• The generate statement
• Signal and variable assignments
• Synthesis of statements
• Latch inference
• For loops & loop synthesis
Simulation and Synthesis
• How a VHDL simulator works
• Event driven simulation
• Event processing
• Simulation (delta) cycles
• Delta cycle race conditions
• Process synthesis
• Synthesisable processes styles & templates
• Combinational logic in a process
• Synchronous (clocked) processes
Finite State Machines (FSMs)
• Review of Moore and Mealy state machines
• Finite state machines representation
• Use of enums to represent state
• FSM code structure
• FSM example (traffic light controller)
• FSM implementation example
• Synthesis of FSMs
Subprograms and Packages
• Subprograms
• Functions
• Procedures
• Differences between functions and procedures
• Subprogram declarations
• Packages
• Package declaration
• Package body
• Example: colour package
Configurable and Scalable Designs
• Generic parameters
• Generic mapping
• Example: generic wordlength
• Configuration declarations
• Default binding
• Example Configuration Declaration
• Assertions
Practical Exercises Undertaken During Course
• Introduction to Mentor Graphics ModelSim for VHDL
• simulation
• Introduction to Xilinx ISE for synthesis & implementation
• 2-bit adder design
• Loadable up-down counter
• Generating regular repetitive structures
• Finite impulse response filter
• Finite state machine
• Post synthesis + post place and route simulation
• RAM board model
• Direct Digital Synthesis (DDS)
Verilog Simulation & Synthesis
Introduction to Verilog
• What is Verilog?
• Scope of Verilog
• Design flow
• Verilog-2001
Verilog Basics
• Modules & ports
• Continuous assignments
• Comments
• Names
• Nets and strengths
• Design hierarchy
• Module instances
• Primitive instances
• Text fixtures
• $monitor
• Initial blocks
• Logic values
• Vectors
• Registers
• Numbers
• Output formatting
• Timescales
• Always blocks
• $stop and $finish
• Using nets and variables correctly
Combinational Logic
• Event control
• If statements
• Begin-endw Incomplete assignment and latches
• Unknown and don’t care
• Conditional operator
• Tristates
• Case, casez and casex statements
• full_case and parellel_case directives
• For, repeat, while and forever loops
• integers
• Self-disabling blocks
• Combinational logic synthesis
Sequential Logic
• Synthesising flip-flops & latches
• Avoiding simulation race hazards
• Nonblocking assignments
• Asynchronous & synchronous resets
• Clock enables
• Synthesizable always templates
• Designing state machines
• State machine architectures
• Verilog code-based FSM strategy
• State encoding
• Unreachable states & safe design practices
• One-hot machines
Other features of Verilog
• Verilog operators
• Part selects
• Concatenation & replication
• Shift registers
• Conditional compilation
• Parameterisation and generate
• Hierarchical names
• Arithmetic operators and their synthesis
• Signed and unsigned values
• Memory arrays
• RAM modelling and synthesis
• $readmemb and $readmemh
Finite State Machines (FSMs)
• Review of Moore and Mealy state machines
• Finite state machines representation
• Use of enums to represent state
• FSM code structure
• FSM implementation example
• Synthesis of FSMs
Tasks and Functions
Subprograms and Packages
• Understanding tasks
• Task arguments
• Task synchronization
• Tasks and synthesis
• Functions
Test Fixtures
• File I/O – Writing to files,Reading from files
• Automated design verification using Verilog
• Force and release
Behavioural Verilog
• Algorithmic coding
• Synchronization using waits & event control
• Concurrent-disabling of always blocks
• Named events
• Fork & join
• Understanding intra-assignment controls
• Blocking and nonblocking assignments
• Continuous procedural assignment
Gate Level Verilog
• Structural Verilog
• Using built-in primitives
• Net types & drive strengths
• net & path delays
• Specify blocks
Verilog for Synthesis with SystemVerilog Synthesis Extensions
Introduction to Verilog and SystemVerilog
• Concepts of top-down design
• Overview of RTL models
• Overview of gate/switch models
Design Verification Using Simulation
• Writing verification testbenches in Verilog
• Running your preferred Verilog simulator
• Debugging designs with simulation
• Lab: running your simulator and debug tools
Verilog HDL Syntax and Semantics
• Identifier names
• Logic values and numbers
• Data types
• SystemVerilog extensions to Verilog data types
• Exercise: selecting the correct data types
Procedures, Programming Statements and Operators
• Procedural blocks
• SystemVerilog enhanced procedural blocks
• Tasks and functions
• Continuous assignments
• Programming statements and operators
• Exercise: programming statement subtleties (“gotchas”)
• Lab: modeling a simple ALU and testbench
Synthesizing RTL Models
• General synthesis guidelines
• Running your preferred synthesis compiler
• Lab: synthesize a shift/storage register
RTL Models of Combinational Logic
• Always procedures and sensitivity lists
• Continuous assignments
• Synthesis full case and parallel case statements
• SystemVerilog unique and priority decision statements
• Lab: model, verify and synthesize an ALU
RTL Models of Sequential Logic
• Flip-flops and latches
• Synchronous and asynchronous inputs
• Lab: model, verify and synthesize a Johnson counter
Modeling State Machines
• Modeling Mealy and Moore state machines
• Modeling state encoding sequences
• SystemVerilog enumerated types
• Lab: model, verify and synthesize a UART
Modeling Structural Netlists—After Synthesis
• Design hierarchy
• Module instantiation
• Generating arrays of instances
• Parameterized models and redefining parameters
• Verilog constructs used in ASIC/FPGA libraries
• Delay calculation and backannotation
• SDF files
• Lab: model and verify a hierarchical design, simulate with SDF delay backannotation
Modeling RAMs and ROMs
• Modeling memories
• Modeling bi-directional ports
• Testing bi-directional ports
• Timing constraints
• Lab: model and verify a dual-port RAM
Design Verification with Verilog
• Design documentation
• Using Verilog as a verification language
• Structured tests
• Configurable test benches
• Writing output files
• Reading test vector files
• Adding built-in error checking
• Lab: verify a design using test vectors
Verilog Wizardry (Lab Intensive Project)
• Using all aspects of Verilog in a design project
• Simulating and verifying larger designs
• Lab: model and verify an embedded DSP processor
SystemVerilog Synthesis for Verilog Design Engineers
Introduction to SystemVerilog
• The purpose of SystemVerilog
• Backward compatibility with Verilog
• Software tools supporting SystemVerilog
Design Hierarchy
• External declarations
• Packages
• Nested modules
• Enhanced module instances
• Parameterized data types
• Lab: Using globals and nested modules
SystemVerilog Data Types and Logic Values
• New data types
• Casting
• User-defined types
• 2-state modeling techniques and “gotchas”
• Lab: Modeling with 2-state data types
Enumerated Types
• Enumerated types
• Specifying label values
• Assignments with enumerated types
• Static and dynamic casting
• Enumerated type methods
• Lab: Modeling a state machine with enumerated types
Arrays, Structures and Unions
• Unpacked arrays
• Packed arrays
• Array querying functions
• Structures
• Unions
• Tagged unions
• Bit-stream casting
• Lab: Using structures, unions and arrays
SystemVerilog procedural blocks
• Combinational logic procedural blocks
• Latched logic procedural blocks
• Sequential logic procedural blocks
• Why specialized procedural blocks are important
• Task and function enhancements
• Passing arguments by reference
• Lab: Using specialized procedures
Programming statements and operators
• New operators
• Enhanced looping constructs
• Bottom testing loops
• New jump statements
• Unique and priority decision statements
• Eliminating simulation versus synthesis mismatches
• Lab: Modeling a high-level ALU
SystemVerilog Interfaces
• Interface definitions
• Defining module ports and directions
• Tasks and functions in interfaces
• Procedural code in interfaces
• Parameterized interfaces
• Verification paradigms with interfaces
• Lab: Using interfaces
Assertions for Design Engineers
• Assertion concepts
• Immediate assertions
• Concurrent assertions and sequences
• Basic sequence definitions
• Disabling assertions during reset
• Controlling assertion messages
• Lab: Using assertions in interfaces
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